1. Field of the Invention
This invention is in the field of semiconductor memory cells, and in particular, an improved memory cell which uses only a single transistor for storage.
2. Prior Art
Single transistor memory cells, sometimes called "two-terminal" transistor memory cells are well known in the art. For example, in the IEEE Journal of Solid-State Circuits, Vol. SC-6, No. 5, October, 1971, pp. 280-283, a description of one such cell appears. This cell uses a single transistor and stores charge on the reverse-biased, back-to-back PN junctions. In operation of this cell, to obtain "charge erasure" (the state in which the capacitors become discharged), at least one PN junction of the transistor must be operated in the avalanche breakdown mode. While using avalanche breakdown to erase the charge is a convenient technique which enables the cell to be built using only a single transistor, it also has certain disadvantages. Lifetime studies have shown that continual avalanching of the junctions causes damage to the junctions and impairs the life of the memory device. Transistor degradation due to repeated breakdown of PN junctions is a well known phenomenon (see D. R. Collins "h.sub.FE Degradation Due to Reverse-Bias Emitter-Base Junction Stress," IEEE Transactions on Electron Devices, Vol. ED-16, April, 1969, pp. 403-406 ). In order to avoid this problem, special types of transistors have been employed in the past. However, such transistors are more difficult to make and have not been capable of reliable large-scale production of large memory arrays.